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CS 232 CS Instruction Sets Question

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Please help me do the questions in the Word document. The pdf file is reference.

Exercise: Instruction sets
1) What is the instruction set:
Answer:
2) Name and explain the two parts that make up an machine code instruction:
Answer:
3) For a word with 4 bits for an opcode and 6 bits for an operand
•
•
How many different instructions could I fit into the instruction set?
What is the largest number that I could use as data?
Answer:
4) For a 16 bit word with 6 bits for an opcode
•
•
How many different instructions could I fit into the instruction set?
What is the largest number that I could use as data?
Answer:
5) Why might a manufacturer choose to increase the instruction set size?
Answer:
6) What might be the problem with increasing the space taken up by the opcode?
Answer:
7) Give two benefits for increasing the word size of a processor?
Answer:
Exercise: Assembly code and Addressing modes
8) For the following memory space, what would it look like after executing the assembly code
below:
Address Contents
10
1
11
4
12
4
13
100
14
5
LOAD 14
ADD #12
STORE 12
Answer:
9) For the following memory space, what would it look like after executing the assembly code
below:
Address Contents
211
6
212
3
213
78
214
21
LOAD #100
STORE 213
LOAD 214
ADD 213
STORE 214
Answer:
10) For the following memory space, what would it look like after executing the assembly code
below:
Address Contents
99
6
100
6
101
8
102
9
LOAD 100
ADD 101
DIV #7
STORE 102
Answer:
11) Write some assembly code to do the following:
34 + 35
and store in memory location 100
Answer:
12) Write some assembly code to do the following:
4 + (100 / 2)
and store in memory location 100
Answer:
13) List and give examples of three addressing modes:
Answer:
Exercise: Machine Code
14) Using the table above provide machine code to do the following:
LOAD 12
ADD #6
Answer:
15) Using the table above give the assembly code for the following machine code:
0001 00000111
0100 00001001
0000 00011110
Answer:
16) Explain what the above code does:
Answer:
17) Convert the following machine code into hexadecimal:
0001
0100
0000
1111
00111011
00001001
00011110
00000000
Answer:
18) If we were lacking Assembly code, why might we want to convert machine code into
Hexadecimal?
Answer:
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2.1 Programmable processor concept
Programmable processor overview
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A programmable processor carries out desired functionality by executing
instructions
from
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instruction memory. Unlike a typical circuit that carries out the same functionality
repeatedly, a
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programmable processor can be con gured to carry out nearly any functionality by putting different
instructions in the instruction memory. Ex: A single programmable processor can be programmed to
carry out the functionality of a calculator, a web browser, and a word processor. Storing instructions
into an instruction memory is known as programming the memory, and those instructions are known
as a program.
The processor executes one instruction at a time, proceeding to the next instruction when done.
PARTICIPATION
ACTIVITY
2.1.1: Simple programmable processor.
Animation captions:
1.
2.
3.
4.
The rst instruction loads t0 with the value located at 5001 from the data memory.
The second instruction loads t1 with the value located at 5002 from the data memory.
The next instruction adds t0 + t1, and puts the sum in t5.
The next instruction stores t5’s value into data memory location 5005.
A programmable processor includes:
CPU: A central processing unit executes instructions by controlling an ALU, register le, and
other hardware components.
ALU: A component that performs arithmetic and logic operations, like addition or
subtraction, on data in the register le. Short for arithmetic logic unit.
Register le: A set of registers that holds temporary data accessible by the ALU. A register
is a digital circuit that can store multiple bits, such as 32 bits.
Instruction memory: A memory that holds instructions.
Data memory: A memory that holds data used by the instructions.
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A memory is a digital circuit that holds relatively large amounts of data, often organized as bytes with
each having a unique address, where each byte can either be read (“load”) or written (“store”). Ex: A
memory may hold 1024 bytes, with addresses 0, 1, 2, …, 1023. Common memory sizes range from 1
Kbyte to 4 Gbyte, while typical register les are smaller with perhaps 128 or fewer registers.
PARTICIPATION
ACTIVITY
2.1.2: Processor basics.
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Refer to the above animation.
1) What is the value in data memory
location 5002?
Check
Show answer
2) What is the value in t1 after the
instruction Load t1 DM[5002]
executes?
Check
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Show answer
3) The rst Add instruction adds the
values in t0 and t1, and writes the result
in what register?
Check
Show answer
4) How many executed instructions
copied data from the data memory to
the register le during the animation?
Check
Show answer
5) How many executed instructions used
the ALU during the animation?
Check
Show answer
6) How many total instructions were
executed during the animation?
Check
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Show answer
7) The CPU contains a register le and
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CS 232: Computer Organization home
what other component?
Check
Show answer
8) A typical register le has 1G or more
registers. Type true or false.
Check
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Show answer
Note that when the processor reads data from the data memory or register le, the data is copied, not
removed.
Instructions
A processor executes instructions in sequence, one at a time. The instruction order thus matters.
PARTICIPATION
ACTIVITY
2.1.3: Instruction order.
1) Complete the following instruction
sequence to add the values in registers
t0 and t1 and store the result in
DM[5007].
_____
Store t6 to DM[5007]
Add t2 = t0 + t1
Add t6 = t0 + t1
Add t6 = t0 + t2
2) Complete the following instruction
sequence to add the values in registers
t2 and t6 and store the result in
DM[5007].
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Add t3 = t2 + t6
_____
Store t6 to DM[5007]
Store t3 to DM[5000]
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Store t3 to DM[5007]
3) Select the instruction sequence that
calculates the sum of register t1 and
DM[5000], and writes the sum in
register t5.
Load t4 with DM[5000]
Add t5 = t1 + t4
Add t5 = t1 + t4
Load t4 with DM[5000]
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4) Select the instruction sequence that
calculates the sum of t0 and t1, and
stores the results to DM[5001].
Store t2 to DM[5001]
Add t2 = t0 + t1
Add t2 = t0 + t1
Store t2 to DM[5001]
A processor may support hundreds of possible instruction types. Those instruction types can usually
be classi ed into three categories:
A data transfer instruction copies data among the data memory and register le.
An ALU instruction operates on data.
A branch instruction speci es the location of the next instruction to execute, being different from
the next instruction in instruction memory.
PARTICIPATION
ACTIVITY
2.1.4: Instruction type categories.
Indicate the category for the instruction.
1) Load t0 with DM[5255]
Data transfer
ALU
Branch
2) Jump to instruction 90
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Data transfer
ALU
Branch
3) Subtract t6 = t1 – t4
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Data transfer
ALU
Branch
Each instruction typically is encoded into a limited number of bits, such as 32 bits. Using a small
limited number of bits per instruction ensures more instructions can t into the memory, and keeps
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the processor’s circuit simple and fast. Some bits may represent the instruction Llesh
type (like
Miraj Load or
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Add), other bits may indicate the registers involved (like t0 or t1), and others
a data memory address
(like 5005). As such, the number of instruction types is limited. Ex: If the instruction type is represented
in 8 bits, then only 28 = 256 instruction types are possible.
Thus, a processor’s instruction types are limited and kept basic, like the basic Add, Store, and Load
instructions seen above. A programmer must achieve desired functionality using just those relativelyfew instruction types.
The set of instruction types supported by a particular processor is called the processor’s instruction
set. A program written using a processor’s instructions is called an assembly language program, in
contrast to programs written in higher-level languages like C, C++, Java, or Python.
PARTICIPATION
ACTIVITY
2.1.5: Using limited instruction types.
Assume a processor’s only instruction type available for adding is:
Add regA = regB + regC
where regA, regB, and regC each is any register.
1) Which computes t5 = t1 + t3?
Add t5 = t1 + t3
Add t1 = t5 + t3
2) Assume the following initial values: t1 =
7, t2 = 6, t3 = 8. What is in t5 after the
following:
Add t0 = t1 + t2
Add t5 = t0 + t3
13
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3
21
3) Assume the following initial values: t1 =
7, t2 = 6, t3 = 8. What is in t5 after the
following:
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Add t3 = t1 + t2
Add t5 = t3 + t3
26
21
4) Which computes t0 = t1 + t2 + t3?
Add t3 = t1 + t2
Add t0 = t3 + t3
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Add t4 = t1 + t2
Add t0 = t4 + t3
5) Which computes t0 = t1 + t2 + t3 + t4?
Add t4 = t1 + t2
Add t0 = t4 + t3
Add t5 = t1 + t2
Add t6 = t3 + t4
Add t0 = t5 + t6
6) Can t4 = t3 + t2 + t1 + t0 be computed
in two instructions?
Yes
No
Register le
Each register in the register le has a name. The zero register is a read-only register that always holds
the value 0. In the animation above, t0 … t6 refer to the register le’s next seven registers, which can be
read and written by instructions.
An ALU instruction may read a register’s value and write the operation’s result into that very same
register.
PARTICIPATION
ACTIVITY
2.1.6: Register le: Reading and writing.
Animation captions:
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1. The instruction adds the values located at t2 and t3.
2. The result overwrites the value in t2 with 70.
PARTICIPATION
2.1.7: Registers.
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ACTIVITY
1) Assume the following initial values: t0 =
7, t1 = 5, and t2 = 3.
What is in t2 after the following:
Add t2 = t2 + t1
3
8
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12
2) Assume the following initial values: t0 =
2, t1 = 5, and t2 = 4. What is in t0 after
the following:
Add t0 = t0 + t1
Add t0 = t0 + t2
2
7
11
3) Assume the following initial values: t2 =
7, t3 = 1, and t4 = 9.
What is in t4 after the following:
Add t3 = t3 + t2
Add t4 = t4 + t3
9
10
17
4) Complete the following instruction
sequence to add the values in registers
t3, t4, and t5, and store the result in
DM[1007].
Add t6 = t4 + t5
_____
Store t6 to DM[1007]
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Add t6 = t6 + t3
Add t6 = t6 + t4
Add t6 = t4 + t3
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Reset
A reset is an input that when asserted causes a circuit to enter a known state. A
processor’s reset causes 0’s to be written to all registers, including the register le and
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program counter. So, after the reset, the processor executes the instruction
at address
Llesh
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0. A power-on-reset circuit resets the processor when power is rst applied.
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Register le and data memory
When displaying data values in registers or memory, this material may show: 1) a 0 for
register if the register is known to be 0, such as on reset, 2) a blank location if the value
is unknown, such as memory location that has not yet been written, or 3) a grayed value
representing a previous value for a register or memory location that has been written a
new value. Additionally, all registers within the register le may not be shown, instead
showing only those registers that are relevant for each example.
MIPS
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MIPS is a processor that was popular in various computers in the 1990’s, and is found in some
embedded computing devices today. MIPS is presently one of the most popular processors for
learning assembly language programming, and also for learning processor design. MIPS is known for
having a simple and elegant instruction set, which in turn enables simple and fast processor designs.
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MIPS’ instruction set has just over 100 instructions, and each instruction is 32 bits. The MIPS register
le has 32 registers, each being 32 bits. Memory addresses are 32 bits. Memory can be accessed by
words (4 bytes), half words (2 bytes), or bytes.
For educational purposes, this material teaches a greatly-simpli ed version of MIPS, known as
MIPSzy, using a small subset of the MIPS instruction set, and using a register le with only 8 primary
registers. MIPSzy only allows memory to be accessed by words (4 bytes).
PARTICIPATION
ACTIVITY
2.1.8: MIPS and MIPSzy.
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1) MIPS is the most popular processor in
commercial products today.
True
False
2) The register le in MIPS has 32
registers.
True
False
3) The register le in MIPSzy has 32
registers.
True
False
Exploring further:
MIPS Processor, Imagination Technologies.
Computer Organization and Design (5e) – Interactive Version (MIPS)
2.2 lw, sw: Load and store instructions
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Load instruction: lw
A load instruction copies data from memory into a register. A MIPS load instruction format is shown
below. Another section discusses the reason for the 0( ) around the memory-address.
lw register 0(memory-address)
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MIPS register names start with a $. MIPSzy supports 8 registers. Writeable registers are $t0, $t1, …,
$t6. A special $zero register always has the value 0 and can only be read, not written.
The load instruction’s memory-address is a register whose value is the memory address from which
data is copied.
Load word
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lw is short for “load word”, in contrast to just loading a byte (a word is four bytes).
PARTICIPATION
ACTIVITY
2.2.1: Load instruction: lw.
1) If $t6’s value is 2020, what is the
memory address for the following
instruction?
lw $t0, 0($t6)
Check
Show answer
2) Given the following register le and
memory contents, what value is loaded
into register $t3 by the following
instruction?
lw $t3, 0($t6)
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Check
Show answer
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3) Given the following register le,
complete the load instruction to load
register $t2 with data at memory
address 5012.
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lw $t2, 0(
Check
)
Show answer
4) Assuming $t5 holds 6000, write a load
instruction that loads register $t4 with
data at memory address 6000.
Check
Show answer
Store instruction: sw
A store instruction copies data from a register to memory. A MIPS store instruction format is shown
below. Another section discusses the reason for the 0( ) around the memory-address.
sw register 0(memory-address)
PARTICIPATION
ACTIVITY
2.2.2: Store instruction: sw.
1) Assuming $t6 holds 600 and $t0 holds
5008, what is the memory address for
the following instruction?
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sw $t6, 0($t0)
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Check
Show answer
2) Given $t2 holds 6200, $t3 holds 536,
and $t4 holds 616, what value is stored
into memory?
sw $t3, 0($t2)
Check
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Show answer
3) Given the following register le,
complete the store instruction to store
register $t2’s value into memory at
address 5000.
sw
, 0($t4)
Check
Show answer
4) Assuming $t0 holds 5400 and $t1
holds 280, write a store instruction that
stores register $t1’s value into memory
at address 5400.
Check
Show answer
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Instruction format summary: lw, sw
The condensed instruction format below speci es all registers using $ followed by a single character.
Ex: $a.
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Table 2.2.1: Instruction summary: lw, sw.
Instruction
Format
lw
Description
lw $a, 0($b)
Example
Load word: Copies data from
memory at address $b to register ©zyBooks
lw $t3,
0($t6)
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$a.
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sw
CHALLENGE
ACTIVITY
sw $a, 0($b)
Store word: Copies data from
register $a to memory at address
$b.
sw $t1, 0($t3)
2.2.1: Load and store instructions.
Start
Compute: $t5 = DM[5580]
lw
$t4
, 0( $t4
)
$t4
$t5
Registers
5580
0
1
Check
View solution
2
Data memory
5580
2
3
Next

(Instructors only)
2.3 Memory alignment and endianness
Memory alignment
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A particular memory may store a sequence of 32-bit wide words (instructions or data). One might
assume addresses for each word would increment by 1, as in: 0, 1, 2, 3, 4, 5, etc. However, each byte in
a word can be addressed individually. Thus, addresses of each word increment by 4: 0, 4, 8, 12, 16, etc.
Memory alignment is the restriction of word addresses to multiples of 4 (or other multiples for
different processors).
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Instructions that load or store words must use addresses that are multiples of four. Instructions that
load or store bytes may use any address.
PARTICIPATION
ACTIVITY
2.3.1: Memory alignment: Because each byte is addressable, word addresses
are multiples of 4.
Animation captions:
1.
2.
3.
4.
5.
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One might assume that word addresses increment by 1.
However, each byte is addressable.
Thus, word addresses increment by 4.
Byte instructions refer only to the indicated byte. Word instructions refer to the entire word.
Word instructions (load or store) must be aligned: Multiples of 4 only.
PARTICIPATION
ACTIVITY
2.3.2: Memory alignment.
Consider the above animation on memory alignment.
1) How many bytes exist per word?
Check
Show answer
2) How many byte addresses exist for one
word?
Check
Show answer
3) What are the byte addresses for the
bytes in the word starting at address
12? Type as: 0, 1, 2, 3
Check
Show answer
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4) Is storing a byte into address 15
allowed? Type yes or no.
Check
Show answer
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5) Is storing a word into address 15
allowed? Type yes or no.
Check
Show answer
6) A programmer wishes to load the last
word of the memory shown in the
animation. What address should be
used in the load word instruction?
Check
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Show answer
Endianness
Endianness refers to whether bytes in a word are ordered starting with the most-signi cant byte rst
(big-endian) or the least-signi cant byte rst (little-endian). Some processors use big-endian format,
others use little-endian.
PARTICIPATION
ACTIVITY
2.3.3: Big-endian vs. little-endian.
Animation captions:
1. An instruction may require one byte for op, one for regA, one for regB, and one for regC (not
real; for example purposes only).
2. Big endian stores the “most-signi cant” byte (op) rst.
3. In contrast, little-endian stores the least-signi cant byte rst.
4. Similarly for binary numbers.
Endianness only impacts the ordering of bytes; the bits within the byte remain in the same order. Ex:
00001111 remains 00001111 for either big or little endian formats, and does not become 11110000.
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Programmers usually need not be concerned with endianness, unless doing byte-level
operations
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within a word (which is rare).
PARTICIPATION
ACTIVITY
2.3.4: Big-endian.
The binary number 00000000 00001111 11111111 11000000 (1048512 in decimal) is to be
stored in word 20 in big-endian format. Indicate the byte address of each byte.
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11000000
11111111
00001111
00000000
20
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21
22
23
Reset
PARTICIPATION
ACTIVITY
2.3.5: Little-endian.
The binary number 00000000 00001111 11111111 11000000 (1048512 in decimal) is to be
stored in word 20 in little-endian format. Indicate the byte address of each byte.
11111111
00000000
11000000
00001111
20
21
22
23
Reset
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PARTICIPATION
ACTIVITY
2.3.6: Endianness.
1) Little-endian processors are faster than
big-endian.
True
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False
2) Programmers spend much time and
effort focusing on endianness.
True
False
3) In little-endian format, 10000000 would
become 00000001.
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True
False
2.4 addi, add: Add instructions
Add with immediate instruction: addi
A program often needs to add a speci c value to a register, such as adding register $t3 and 4. An add
immediate (addi) instruction adds a register’s value and an immediate value. An immediate is a value
speci ed within an instruction. In MIPS, the immediate is a 16-bit number that can range from -32,768
to 32,767. A MIPS addi instruction format is shown below, which computes regA = regB + immediate.
addi regA, regB, immediate
PARTICIPATION
ACTIVITY
2.4.1: Add immediate (addi) instruction.
Animation captions:
1. The add immediate instruction adds the immediate value 4 to the value held in $t0. The sum is
written to register $t1.
2. An immediate value can be negative. -10 is added to the value held in $t2, and the result 40 +
-10 or 30 is written to $t3.
PARTICIPATION
ACTIVITY
2.4.2: addi instruction.
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For each question, assume initial register values of:
$t0: 20
$t1: 50
$t2: 60
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1) After the following, what is $t4?
addi $t4, $t2, 1
Check
Show answer
2) After the following, what is $t3?
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addi $t3, $t1, -5
Check
Show answer
3) After the following, what is $t2?
addi $t2, $t2, 6
Check
Show answer
4) Type an addi instruction that writes $t5
with the sum of $t4 and 17.
Check
Show answer
5) Type an instruction that adds 3 to $t4,
writing the sum to $t4.
Check
Show answer
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Commonly, a speci c value needs to be written to a register. The addi instructionLlesh
format
Mirajbelow
PACECS232MirajSpring2021
computes regA = immediate:
addi regA, $zero, immediate
Since $zero always holds the value 0, the sum is equal to the immediate value, and the immediate
value is written to the register.
PARTICIPATION
ACTIVITY
2.4.3: Initializing registers with addi.
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Given the following register le contents, match the register to the value held in the register
as the provided instructions.
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addi $t4, $zero, 40
addi $t3, $t0, 0
addi $t2, $zero, 50
20
50
40
$t2
$t3
$t4
Reset
Add instruction: add
An add instruction computes the sum of two register values, and writes the sum into a register. A
MIPS add instruction format is shown below, which computes regA = regB + regC.
add regA, regB, regC
The register written by an instruction is called the destination register.©zyBooks
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instruction is called a source register. For the add instruction, regA is thePACECS232MirajSpring2021
destination register, and regB
and regC are source registers.
PARTICIPATION
ACTIVITY
2.4.4: Add instruction.
Assume initial register values of
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$t0: 20
$t1: 30
$t2: 40
1) After the following, what is $t0?
add $t0, $t1, $t2
Check
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Show answer
2) After the following, what is $t2?
add $t0, $t1, $t2
Check
Show answer
3) After the following, what is $t2?
add $t2, $t1, $t0
Check
Show answer
4) After the following, what is $t2?
add $t2, $t0, $t1
Check
Show answer
5) Type an instruction that writes $t3 with
the sum of $t5 and $t6.
Check
Show answer
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Table 2.4.1: Instruction summary: addi, add.
Instruction
addi
Format
Description
addi $a, $b, C
Add immediate: Adds register
$b and the immediate value
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Example
addi $t3, $t2, 7
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C, and writes the sum into
register $a.
add
Add: Computes the sum of
registers $b and $c, and
writes the sum into register
$a.
add $a, $b, $c
add $t4, $t1, $t2
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CHALLENGE
ACTIVITY
2.4.1: Add immediate and add instructions.
Start
Compute: $t3 = $t4 + 3
addi
$t3
,
$t3
,
0
$t3
$t4
1
2
Check
View solution
Registers
0
2
3
4
Next

(Instructors only)
2.5 Comments
A comment is text in a program intended just for humans reading the program, rather than for the
processor executing the program. In MIPS, a comment is any text on a line following the # symbol.
lw $t1, 0($t6)
# This is a comment
add $t1, $t1, $t1 # Another comment
# And yet another comment
PARTICIPATION
ACTIVITY
2.5.1: Comments.
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Given the following code, indicate which is a comment.
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lw $t2, 0($t6) # Load DM[2000]
# add $t2, $t3, $t4
# FIXME: Finish the
program soon
#####
# 6/3/16
1) lw
Comment
Not a comment
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2) Load DM[2000]
Comment
Not a comment
3) add $t2, $t3, $t4
Comment
Not a comment
4) FIXME: Finish the
Comment
Not a comment
5) program soon
Comment
Not a comment
6) ####
Comment
Not a comment
7) 6/3/16
Comment
Not a comment
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2.6 A small assembly program
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Creating and executing a small program
Given desired behavior, a programmer must create an instruction sequence implementing such
behavior, using only the processor’s available instructions.
PARTICIPATION
ACTIVITY
2.6.1: Creating and executing a small program.
Animation captions:
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1. A sequence of instructions are speci ed to implement the desired goal.
2. The addi instruction is used to initialize $t4, $t5, and $t6 with the memory addresses 5020,
5024, and 5032, respectively.
3. $t4 and $t5 hold the memory addresses 5020 and 5024. The data in memory address 5020
and 5024 is copied into registers $t0 and $t1, respectively.
4. The sum of registers $t0 and $t1 is computed, and then written into register $t2.
5. The data in register $t2 is copied to memory at address 5032.
6. Executing the program illustrates that the desired goal is met: DM[5032] = DM[5020] +
DM[5024].
PARTICIPATION
ACTIVITY
2.6.2: Creating small programs.
Indicate the WRONG item. DM refers to data memory. Assume initial values:
$t0: 5000
$t1: 5004
$t2: 5008.
1)
Desired behavior: DM[5000] = DM[5004] +
DM[5008]
lw $t3, 0($t1) # Load DM[5004]
lw $t4 , 0($t2) # Load DM[5008]
add $t5, $t3 , $t4 # Add DM[5004] + DM[5008]
sw $t5, 0( $t1 ) # Store result into DM[5000]
2)
Desired behavior: DM[5000] = DM[5000] +
DM[5004]
lw $t3, 0($t0)
lw $t4, 0( $t2 )
add $t3 , $t3, $t4
sw $t3, 0(
3)
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$t0 )
Desired behavior: DM[5008] = DM[5004] +
DM[5004] + DM[5004]
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lw $t3, 0($t1)
add $t4, $t3, $t3
add $t4, $t4, $t4
sw $t4, 0($t2)
PARTICIPATION
ACTIVITY
2.6.3: Load, store, and memory.
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1. Run the simulation step-by-step, observing memory values.
2. Change DM[5000]’s value to 45 by clicking the memory value on the right, then run
again.
3. Store the addition result in DM[5004] by appending sw $t2, 0($t4)
Assembly
Line
Line
Line
Line
Line
Line
1
2
3
4
5
6
addi $t3, $zero, 5000 # initialize $t3
addi $t4, $zero, 5004 # initialize $t4
lw $t0, 0($t3)
# Load DM[5000]
lw $t1, 0($t4)
# Load DM[5004]
add $t2, $t0, $t1 # Add DM[5000] and DM[5004]
Registers
$zero
0
Data mem
5000
3
$t0
0
5004
5
$t1
0
5008
$t2
0
$t3
0
$t4
0
+
+
ENTER SIMULATION
STEP
RUN
More options
Conserving registers in assembly programs
Registers are limited, so programmers should conserve registers. If a value in a register is not read
later, the register can be reused by writing another value. Ex: Assume $t4
holds a02/03/21
memory
address
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Miraj
used in a lw instruction. If that memory address is not used by another instruction, $t4 can be reused
PACECS232MirajSpring2021
to hold a different memory address or used to hold the result of a computation.
PARTICIPATION
ACTIVITY
2.6.4: Conserving registers.
Animation captions:
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1. $t4, $t5, and $t6 are initialized with the memory addresses 5020, 5024, and 5032. Each of the
addresses is only used once, and a single register could be used.
2. For each lw and sw instruction, an addi instruction initializes $t4 with the memory address.
The following lw or sw instruction uses $t4 to access memory.
PARTICIPATION
ACTIVITY
2.6.5: Conversing register in assembly programs.
1) Which register can be reused in the
addi and sw instructions to store $t6 to
memory address 5048?
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addi $t2, $zero, 5048
lw $t4, 0($t2)
add $t6, $t6, $t4
sw $t6, 0(___)
$t2
$t6
2) Which register can be reused in the
addi and lw instructions to load $t5
with data at memory address 5012?
addi $t1, $zero, 5000
lw $t4, 0($t1)
addi $t2, $zero, 5008
lw $t5, 0($t2)
addi ___, $zero, 5012
lw $t6, 0(___)
add $t4, $t4, $t5
sw $t4, 0($t2)
$t1
$t2
3) If the add instruction’s destination
register is changed from $t3 to $t2,
what other instruction must be
updated?
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addi $t4, $zero, 5020
lw $t1, 0($t4)
addi $t4, $zero, 5024
lw $t2, 0($t4)
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add $t3, $t2, $t1
addi $t4, $zero, 5032
sw $t3, 0($t4)
lw $t2, 0($t4)
sw $t3, 0($t4)
PARTICIPATION
ACTIVITY
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2.6.6: Conserving registers used for memory addresses.
PACECS232MirajSpring2021
The program below computes DM[5000] = DM[5000] + DM[5004] + DM[5008]
1. Run the simulation step-by-step, observing that program uses $t4, $t5, and $t6 for the
three memory addresses 5000, 5004, and 5008.
2. Revise the program to only use $t4 for the memory addresses. Before each lw or sw
instruction, add an addi instruction to initialize $t4 with the memory address. Then, use
$t4 in the lw or sw instructions.
Assembly
Line
Line
Line
Line
Line
Line
Line
Line
Line
1
2
3
4
5
6
7
8
9
addi $t4, $zero, 5000 # initialize $t4
addi $t5, $zero, 5004 # initialize $t5
addi $t6, $zero, 5008 # initialize $t6
lw $t0, 0($t4)
# Load DM[5000]
lw $t1, 0($t5)
# Load DM[5004]
lw $t2, 0($t6)
# Load DM[5008]
add $t3, $t0, $t1 # Add DM[5000] and DM[5004]
add $t3, $t3, $t2 # Add sum and DM[5008]
sw $t3, 0($t4)
# Store sum to DM[5000]
Registers
$zero
0
Data mem
5000
$t0
0
5004
$t1
0
5008
$t2
0
$t3
0
$t4
0
$t5
0
$t6
0
2
+
+
ENTER SIMULATION
STEP
RUN
More options
CHALLENGE
ACTIVITY
2.6.1: Load, store, add, and addi instructions.
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Start
Compute: DM[6732] = $t5 + DM[5688]
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lw
$t3
, 0( $t3
)
lw
$t3
, 0( $t3
)
lw
$t3
, 0( $t3
)
$t3
$t4
$t5
$t6
Registers
6732
0
6
5688
1
Check
View solution
2
Next

Data memory
5688
7
6732
0
3
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(Instructors only)
2.7 sub, mul: Subtraction and multiplication
instructions
Subtract instruction: sub
A subtract instruction (sub) computes the difference of two register values, and writes the difference
into a register. A MIPS subtract instruction format is shown below, which computes regA = regB regC.
sub regA, regB, regC
PARTICIPATION
ACTIVITY
2.7.1: sub instruction.
Assume initial register values of:
$t0: 30
$t1: 10
$t2: -5
$t3: 5
1) After the following, what is $t4?
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sub $t4, $t1, $t3
Check
Show answer
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2) After the following, what is $t0?
sub $t0, $t0, $t3
Check
Show answer
3) After the following, what is $t5?
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sub $t5, $t1, $t2
Check
Show answer
4) Type an instruction to subtract $t3
from $t4, writing the difference to $t5.
Check
Show answer
Multiply instruction: mul
A multiply instruction (mul) computes the product of two register values, and writes the product into a
register. A MIPS multiply instruction format is shown below, which computes regA = regB * regC. The
multiply instruction computes a 32-bit product, and ignores any over ow that may result from
multiplying two 32-bit values.
mul regA, regB, regC
PARTICIPATION
ACTIVITY
2.7.2: mul instruction.
Assume initial register values of:
$t0: 40
$t1: 20
$t2: 70000
$t3: 30
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1) After the instruction mul $t3, $t1,
$t0 what is $t3?
600
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800
2) Which instruction multiplies $t4 with
$t5, writing the product to $t5.
mul $t5, $t5, $t4
mul $t4, $t5, $t5
3) Does the following instruction result in
an over ow?
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mul $t5, $t1, $t2
Yes
No
4) Does the following instruction result in
an over ow?
mul $t5, $t2, $t2
Yes
No
Pseudoinstructions
A native instruction is an assembly instruction directly supported by a processor’s
hardware. A pseudoinstruction is an assembly instruction that must be replaced by one
or more native instructions before being executed. Pseudoinstructions are used to keep
the number of native instructions small, which leads to more e cient processor
hardware, while providing programmers a large set of instructions for common
operations. The MIPS mul instruction is a pseudoinstruction implemented using mult
and m o native instructions, discussed elsewhere.
PARTICIPATION
ACTIVITY
2.7.3: sub and mul instructions.
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The assembly program below calculates the total taxi fare as $15 plus $2 per mile traveled.
DM[5000] holds the total miles traveled, and the total fare is stored in DM[5004].
1. Run the simulation step-by-step, observing memory values.
2. Change DM[5000]’s value to 25, then run again.
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3. Modify the program to subtract $2 for a frequent rider discount, store the discounted
total fare in DM[5008].
Assembly
Line
Line
Line
Line
Line
Line
Line
1
2
3
4
5
6
7
addi $t5, $zero, 5000
lw $t0, 0($t5)
addi $t1, $zero, 2
mul $t2, $t0, $t1
addi $t2, $t2, 15
addi $t5, $zero, 5004
sw $t2, 0($t5)
Registers
$zero
$t0
Data mem
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0
PACECS232MirajSpring2021
5004
$t1
0
$t2
0
$t5
0
5008
+
+
ENTER SIMULATION
STEP
RUN
More options
Instruction format summary: sub, mul
Table 2.7.1: Instruction summary: sub, mul.
Instruction
sub
mul
Format
Description
Example
sub $a, $b, $c
Subtract: Subtracts $c from
$b, and writes the difference
into register $a.
mul $a, $b, $c
Multiply: Multiplies register $b
and $c, and writes the lower
mul $t3, $t2, $t1
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32-bits of the product into
Llesh Miraj
register $a.
sub $t3, $t2, $t5
PACECS232MirajSpring2021
CHALLENGE
ACTIVITY
2.7.1: Subtract and multiply instructions.
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Start
Compute: $t3 = $t5 – $t4
sub
$t3
,
$t3
,
Registers
$t3
$t3
$t4
$t5
1
2
Check
View solution
0
6
3
3
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4
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Next

(Instructors only)
2.8 beq, bne, j: Branch and jump instructions
Branch instructions: beq, bne
A branch instruction speci es the location of the next instruction to execute, depending on the branch
instruction’s condition. A branch on equal (beq) instruction branches to an instruction at a speci ed
location if the values held in two registers are equal. If the values are equal, the branch is taken, and
the instruction at the speci ed location is executed. Otherwise, the branch is not taken, and the
instruction immediately following the branch instruction is executed.
A branch instruction typically uses a label to specify the next instruction’s location. A label is a named
position in a program that represents an instruction’s memory address. The MIPS beq instruction
format below branches to the instruction at location Label if the values held in regA and regB are
equal.
beq regA, regB, Label
A label is a sequence of letters (a-z, A-Z, _) and digits (0-9) starting with a letter and followed by a
colon (:).
PARTICIPATION
ACTIVITY
2.8.1: Branch on equal (beq) instruction.
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Animation captions:
1. The beq instruction compares the values held in $t1 and $t0. 5 is equal to 5, so the execution
will branch to the instruction following the label Cont.
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2. The label Cont represents the addi instruction’s memory address. Labels allow a program to
branch to instructions without yet knowing the instruction’s address.
3. Execution continues with the addi instruction. The add instruction was not executed, because
the branch was taken.
PARTICIPATION
ACTIVITY
2.8.2: beq instruction.
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Which instruction is executed immediately after the branch instruction.
Assume initial register values of:
$t0: 5
$t1: 10
$t2: 0
$t3: 10
beq $t1, $t3, Cont
1)
sub $t1, $t1, $t5
Cont: sw $t4, 0($t6)
beq $t0, $t1, Cont
2)
sw $t1, 0($t5)
Cont: addi $t1, $t1, -2
beq $t2, $zero, Cont
3)
addi $t4, $t4, 11
sw $t4, 0($t6)
Cont: lw $t2, 0($t6)
beq $t3, $t1, Cont
4)
addi $t3, $t3, 2
Cont:
sub $t3, $t3, $t5
PARTICIPATION
ACTIVITY
2.8.3: Labels.
Which are valid labels for the addi instruction?
1)
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Cont: addi $t2, $t2, 1
Valid
Invalid
2)
After_Adjust: addi $t2, $t2,
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1
Valid
Invalid
3)
userValEq3: addi $t2, $t2, 1
Valid
Invalid
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4)
IsGood?: addi $t2, $t2, 1
Valid
Invalid
5)
Grade equals 100: addi $t2,
$t2, 1
Valid
Invalid
6)
CheckResult:
addi $t2, $t2, 1
Valid
Invalid
7)
2ndTask: addi $t2, $t2, 1
Valid
Invalid
A branch on not equal (bne) instruction branches to an instruction at a speci ed location if the values
held in two registers are not equal. The MIPS bne instruction format below branches to the instruction
at Label if the values held in regA and regB are not equal.
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bne regA, regB, Label
PARTICIPATION
ACTIVITY
Llesh Miraj
PACECS232MirajSpring2021
2.8.4: Branch instructions: bne and beq.
For each question, assume initial register values of:
$t0: 20
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$t1: 15
$t2: 15
$t3: 21
1) After the following, what is $t3?
bne $t0, $t1, Cont
addi $t3, $t3, 5
Cont: addi $t2, $t2, 2
Check
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Show answer
2) After the following, what is $t3?
bne $t1, $t2, Cont
addi $t3, $t3, 7
Cont: addi $t2, $t2, 3
Check
Show answer
3) After the following, what is $t2?
bne $t1, $t2, Cont
addi $t3, $t3, 7
Cont: addi $t2, $t2, 3
Check
Show answer
4) After the following, what is $t3?
bne $t2, $t1, Cont
addi $t3, $t3, 8
Cont: addi $t3, $t3, 4
Check
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Show answer
5) How many instructions execute in the
following?
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bne $t2, $t0, Cont1
addi $t3, $t3, 8
Cont1:
bne $t2, $t1, Cont2
addi $t3, $t3, 5
Cont2:
addi $t3, $t3, 7
Check
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Show answer
Jump instruction
A jump (j) instruction speci es the location of the next execution to execute. A jump instruction is also
known as an unconditional branch. The MIPS j instruction format below jumps to the instruction at
Label.
j Label
PARTICIPATION
ACTIVITY
2.8.5: Jump (j) instruction.
Animation captions:
1. The jumps instruction speci es the location of the next execution to execute, so the addi
instruction is executed after the jump.
PARTICIPATION
ACTIVITY
2.8.6: Jump instructions.
1) A jump instruction will always jump to
the labeled instruction.
True
False
2) A jump instruction can only jump to a
labeled instruction located after the
jump instruction.
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True
False
3) Which instruction is executed after the
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jump instruction?
j Comp2
Comp1: addi $t2, $zero, -5
Comp2: sw $t3, 0($t5)
addi
sw
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Branch and jump instructions are commonly used together to direct a program
to conditionally
execute either one group of instructions or another group, but not both. A branch instruction is used to
decide which group of statements to execute. If the branch is taken, the instruction group at the label
speci ed in the branch is executed. If the branch is not taken, the instruction group after the branch is
executed. That instruction group ends with a jump instruction to the rst instruction after the other
instruction group, so the other instruction group is not executed.
PARTICIPATION
ACTIVITY
2.8.7: Using branch and jump instructions to execute one of two instruction
groups.
Animation captions:
1.
2.
3.
4.
If the branch is taken, the instruction group at the label Equal is executed.
Then, execution continues with the instructions after the label After.
If the branch is not taken, the instruction group after the branch instruction executed.
The jump instruction jumps to the label After, which is after the instructions that would
execute if the branch was taken. So, only one of the instruction groups is executed.
PARTICIPATION
ACTIVITY
2.8.8: Branch and jumps instructions.
Refer to the animation above.
1) Assume initial register values of $t1: 4,
$t2: 7.
How many instructions are executed?
Check
Show answer
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2) Assume initial register values of $t1:
10, $t2: 10.
How many instructions are executed?
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Check
Show answer
3) Assume initial register values of $t0: 5,
$t1: 10, $t2: 10, $t3: 20.
What is $t3 when execution reaches
the label After?
Check
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Show answer
4) Assume initial register values of $t0: 5,
$t1: 4, $t2: 18, $t3: 20.
What is $t3 when execution reaches
the label After?
Check
PARTICIPATION
ACTIVITY
Show answer
2.8.9: Branch and jump instruction example.
The assembly program below adds 5 to DM[5004] if DM[5000] is 100. Otherwise, the
program adds 10 to DM[5004]. The sum is stored in DM[5008].
1. Run the simulation step-by-step, observing memory values.
2. Change DM[5000]’s value to 95, then run again.
3. Modify the program to add 5 to DM[5004] if DM[5000] is 100, add 10 if DM[5000] is 95,
and add 20 otherwise.
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Assembly
Line 1
addi $t5, $zero, 5000
Line 2
lw $t0, 0($t5)
# Load DM[5000]
Line 3
addi $t5, $zero, 5004
Line 4
lw $t1, 0($t5)
# Load DM[5004]
Line 5
addi $t2, $zero, 100
Line 6
bne $t0, $t2, Add10
Line 7
addi $t1, $t1, 5 # Add 5
Line 8
j After
Line 9 Add10:
Line 10
addi $t1, $t1, 10 # Add 10
Line 11 After:
Line 12
addi $t5, $zero, 5008
Line 13
sw $t1, 0($t5)
# Store sum to DM[5008]
Registers
$zero
0
5000
10
$t0
0
5004
6
$t1
0
5008
$t2
$t3
Data mem
0
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0
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$t4
0
$t5
0
+
ENTER SIMULATION
STEP
RUN
More options
Table 2.8.1: Instruction summary: beq, bne, j.
Instruction
beq
bne
Format
Description
beq $a, $b, BLabel
Branch on
equal:
Branches to
the
instruction
at BLabel if
the values
held in $a
and $b are
equal.
Otherwise,
instruction
immediately
after beq is
executed.
bne $a, $b, BLabel
Branch on
not equal:
Branches to
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Example
beq $t3, $t2, SumEq5
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bne $t4, $t5, GuessNeqCorrect
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the
instruction
at BLabel if
the values
held in $a
and $b are
not equal.
Otherwise,
instruction
immediately
after bne is
executed.
j
Jump:
Causes
execution to
continue
with the
instruction
at JLabel.
j JLabel
CHALLENGE
ACTIVITY
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j CalcTip
2.8.1: Branch and jump instructions.
Start
Convert pseudocode to MIPS:
if ($t1 != $t2)
$t3 = $t3 + $t3;
add
$t3
,
$t3
,
$t3
add
$t3
,
$t3
,
$t3
L1:
1
2
Check
View solution
3
4
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5
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Next

(Instructors only)
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2.9 slt: Set on less than instruction
Set on less than instruction
The set on less than (slt) instruction sets a register to 1 if the value held in the register is less than the
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value held in another register , otherwise the register is set to 0. Ex: slt
$t1, $t4, $t5 sets $t1 to
Llesh Miraj
1 if $t4’s value is less than $t5’s value, otherwise $t1 is set to 0. The slt instruction
is typically used
PACECS232MirajSpring2021
with the beq or bne instructions to branch to an instruction based on the relational comparisons to
two registers.
PARTICIPATION
ACTIVITY
2.9.1: Set on less than instruction.
Animation captions:
1. The slt instruction compares the values held in $t0 and $t1. 5 is less than 10, so $t2 is “set” by
writing 1 to $t2.
2. $t2 and $zero are not equal, so the bne instruction branches to BLabel.
PARTICIPATION
ACTIVITY
2.9.2: Set on less than.
Assume initial register values of:
$t0: 40
$t1: 20
$t2: 55
1) What is $t5 after the instruction below?
slt $t5, $t0, $t2
0
1
2) What is $t5 after the instruction below?
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slt $t5, $t2, $t1
0
1
3) Determine if the branch instruction is
taken or not taken.
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slt $t4, $t0, $t2
beq $t4, $zero, BLabel
Taken
Not taken
4) Determine if the branch instruction is
taken or not taken.
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slt $t5, $t0, $t1
beq $t5, $zero, BLabel
Taken
Not taken
5) Determine if the branch instruction is
taken or not taken.
slt $t6, $t1, $t2
bne $t6, $zero, BLabel
Taken
Not taken
Branch pseudoinstructions: blt, ble, bgt, bge
Common comparisons used for branch instructions include less than (), and greater than or equal (≥). However, MIPS natively supports only two branch
instructions: beq (branch on equal) and bne (branch on not equal). An slt followed by either a beq or
bne can implement any comparison , ≥. However, the slt + beq/bne approach is non-intuitive to
many programmers. Thus, MIPS supports the following pseudoinstructions.
A branch on less than (blt) instruction branches if the rst register is less than the second.
A branch on less than or equal (ble) instruction branches if the rst register is less than or equal
to the second.
A branch on greater than (bgt) instruction branches if the rst register is greater than the
second.
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A branch on greater than or equal (bge) instruction branches if the rst register
is greater than or
PACECS232MirajSpring2021
equal to the second.
A MIPS assembler will convert each pseudoinstruction into the indicated two native instructions. The
assembler uses a temporary register to store the result of an slt instruction, which is used in the
following beq or bne instruction. The $at (or assembler temporary) register is reserved for use by the
assembler to hold temporary values needed to implement pseudoinstructions.
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Table 2.9.1: Branch pseudoinstructions and
equivalent native instructions.
Branch pseudoinstruction
Native instructions
blt $t0, $t1, BLabel
slt $at, $t0, $t1
bne $at, $zero, BLabel
ble $t0, $t1, BLabel
slt $at, $t1, $t0
beq $at, $zero, BLabel
bgt $t0, $t1, BLabel
slt $at, $t1, $t0
bne $at, $zero, BLabel
bge $t0, $t1, BLabel
slt $at, $t0, $t1
beq $at, $zero, BLabel
PARTICIPATION
ACTIVITY
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2.9.3: Branch pseudoinstructions.
Refer to the above table.
1) beq is a pseudoinstruction.
True
False
2) slt is a native instruction.
True
False
3) A blt $t0, $t1 is replaced by an slt $at,
$t0, $t1 followed by a bne.
True
False
4) A bgt $t0, $t1 is replaced by an slt $at,
$t0, $t1 followed by a bne.
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True
False
5) A bge $t0, $t1 is replaced by an slt $at,
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$t0, $t1 followed by a beq.
True
False
6) A ble $t0, $t1 is replaced by an slt $at,
$t1, $t0 followed by a beq.
True
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False
Table 2.9.2: Instruction summary: slt.
Instruction
Format
slt
CHALLENGE
ACTIVITY
Description
slt $a, $b, $c
Example
Set on less than: Write 1 to
register $a if value held in
register $b is less than value
held in register $c, and
otherwise writes 0.
slt $t1, $t5, $t6
2.9.1: Set on less than, and branch pseudoinstructions.
Start
Implement bgt to branch when $t3 > $t4.
slt
$t3
,
$t3
,
$t3
bne
$at
,
$zero
,
L1
add
$t5
,
$t5
,
$t5
L1:
1
Check
View solution
2
$t3
$t4
$t5
Registers
1
2
5
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
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2.10 Input / output
To be useful, a computer system needs to produce output that a user can examine. Ex: A program that
outputs a table of powers of 2 (1, 2, 4, 8, 16, …) needs a way to provide that table to a user. Typical
output methods include screens and les. MIPSzy uses the following simple output approach:
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To output an integer, a program writes the integer to memory location 8200.
Llesh Miraj
Special hardware detects a write to location 8200, and automatically
outputs that integer to a
PACECS232MirajSpring2021
screen.
Likewise, a computer system needs to accept user input. Ex: A program may accept user input, then
output 2 times that input. Typical input methods include keyboards and les. MIPSzy uses the
following simple input approach:
When input is available, special hardware puts the next input value into memory location 8196,
and sets location 8192 with 1.
A program can load from location 8196 to get the next input value (typically after checking that
location 8192 is 1). The hardware detects such a load, and automatically puts the next input
value into 8196 (or if no further input exists, sets 8192 with 0).
PARTICIPATION
ACTIVITY
2.10.1: MIPSzy output and input: Stores to 8200 are also automatically output
to the screen. Input is automatically put in 8196.
Animation captions:
1. For output, the program stores an integer at location 8200. Special hardware automatically
outputs that integer to the screen at the current cursor position.
2. For input, special hardware puts an input integer in location 8196, and puts 1 in 8192
indicating an input value is ready.
3. A program can load 8196 to get the input value. The hardware detects the load and
automatically puts the next input value into 8196 (or if no more input, sets 8192 with 0).
The program below outputs the rst few powers of 2 (1, 2, 4, 8) to the screen.
PARTICIPATION
ACTIVITY
2.10.2: MIPSzy output.
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Assembly
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 11
addi $t0, $zero, 8200 # Output l
addi $t1, $zero, 2 # Constant
addi $t2, $zero, 1
sw $t2, 0($t0) # Output to scree
mul $t2, $t2, $t1 # Times 2
sw $t2, 0($t0) # Output to scree
mul $t2, $t2, $t1 # Times 2
sw $t2, 0($t0) # Output to scree
mul $t2, $t2, $t1 # Times 2
sw $t2, 0($t0) # Output to scree
Registers
$zero
0
8192
0
InputReady
8200
8196
0
InputValue
$t0
$t1
2
$t2
8
Data memory
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8200
OutputValu
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8 Miraj
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+
+
ENTER SIMULATION
STEP
RUN
More options
PARTICIPATION
ACTIVITY
2.10.3: MIPSzy output.
1) To output 9 to the screen, a program
should store 9 into memory location
_____ .
8192
8200
2) If a program should output 3 2 1 to the
screen, the program should store 3 in
8200, 2 in 8204, and 1 in 8208.
True
False
3) To output the letter ‘c’ on the screen,
the program should store the ASCII
value of ‘c’, namely 99, into location
8200.
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True
False
The program below reads input values as long as another value exists, outputting 2 times each value.
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PARTICIPATION
ACTIVITY
2.10.4: Input and output.
Assembly
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line 7
Line 8
Line 9
Line 10
Line 11
Line 12
Line 13
addi $t1, $zero, 8192
GetIn: lw $t3, 0($t1) # Kb ready
beq $zero, $t3, Done
Registers
$zero
0
Data memory
5000
0
$t0
addi $t2, $zero, 8196
lw $t4, 0($t2) # Get Kb input
0
5004
$t1
8192
5008
0
add $t4, $t4, $t4 # Double
$t2
8196
8192
1
InputReady
addi $t5, $zero, 8200
sw $t4, 0($t5) # Output double t
j GetIn
Done:
$t3
1
8196
-3
InputValue
$t4
-6
8200
0
OutputValu
$t5
8200
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+
+
ENTER SIMULATION
STEP
RUN
More options
PARTICIPATION
ACTIVITY
2.10.5: MIPSzy input.
1) An input integer from a keyboard is
automatically placed by special
hardware into memory location _____ .
8192
8196
2) A program _____ store values into 8196
using sw instructions.
should
should not
3) When a program loads a value from
8196, the hardware automatically puts
the next input value into 8196.
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True
False
4) If 8192 holds 0, then 8196 ____ the next
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input value.
has
does not have
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