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I have some questions that I need help solving!I have attached files with similar questions that I have.

Question 1: 25%
Sketch the output waveforms for the following diode circuits assuming the input voltage source is a
sine wave with 9V amplitude, and the diode has constant 0.7V turn-on voltage. Label peak and
valley of the output voltage waveforms at steady state, based on two sine wave cycles as input.
i)
ii)
iii)
iv)
(Page 3 / 6)
Question 2: 25%
a) Consider a half-wave peak rectifier fed by a 100-Hz sinusoid having a peak value Vp = 100 V.
Assume the load resistance R = 10 kΩ and the diode is ideal.
(4×5=20%)
i) Find the value of the capacitance C that will result in a peak-to-peak ripple of 0.5 V.
ii) Calculate resistor current IL.
iii) Peak diode current iD.
iv) If the capacitance of the output filter capacitor C is halved, what is the new peak diode current
iD?
(Page 4 / 6)
Question 3: 25%
a) Given that a NMOS has VTN=0.7V, complete the table given. Operation region can be either cut
off, triode or saturation.
(10%)
(b) In the given circuit below, assume that Q1 and Q2 are matched except for having different widths,
W1 and W2. Let VTN=0.5V, kn’=0.5mA/V2, L1=L2=0.5μm, W1=1.5μm, and λ=0.
(i) Find the value of VD1 and R required to establish a current of 50 μA in Q1.
(5%)
(ii) Find W2 and R2 so that Q2 operates at the edge of saturation with a current of 150 μA.
(5%)
(Page 5 / 6)
Question 4: 25%
Please circle the correct answer. Each sub-question carries 5%, total grade for this question is
capped at 20%.
a) Peak inverse voltage (PIV) requirement of a diode in a full wave 2-terminal transformer bridge
rectifier is higher than a diode in a full wave 3-terminal center tapped transformer rectifiers.
TRUE
/
FALSE
b) When the output ripple voltage of a rectifier is increased by decreasing the filter capacitor, the
peak diode current reduces.
TRUE
/
FALSE
c) When we design MOSFET circuits, we should choose minimum channel length allowed in the
process for analog circuits, but larger length for digital circuits for the best circuit performance.
TRUE
/
FALSE
d) With similar biasing voltages, if both PMOS and NMOS are having the same drain current, the
chip area occupied by a PMOS is smaller than a NMOS.
TRUE
/
FALSE
e) When a NMOS transistor DC biasing drain current is increased, the NMOS transistor output
resistance rO is decreased.
TRUE
(Page 6 / 6)
/
FALSE
EE330 – Homework 4 (Due: 3/31/2021 Wednesday via Canvas)
First Name:
Last Name:
Red ID#:
Kindly note that no late submission will be accepted.
4.1 A circuit designer intending to operate a MOSFET in saturation is considering the effect of
changing the device dimensions and operating voltages on the drain current ID. Specifically, by what
factor does ID change in each of the following cases?
(a) The channel length is doubled.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
(e) Changes (a), (b), (c), and (d) are made simultaneously.
4.2 An NMOS transistor is fabricated in a 0.4-μm process having μnCox = 200 μA/V2 and VA’ = 50
V/μm of channel length.
(a) If L = 0.8 μm and W = 16 μm, find VA and λ.
(b) Find the value of ID that results when the device is operated with an overdrive voltage VOV = 0.5
V and VDS = 1 V.
(c) Also, find the value of ro at this operating point.
(d) If VDS is increased by 2 V, what is the corresponding change in ID?
4.3 In the given circuit below, assume that Q1 and Q2 are matched except for having different widths,
W1 and W2. Let Vt=0.5V, kn’=0.4mA/V2, L1=L2=0.36μm, W1=1.44μm, and λ=0.
(a) Find the value of VD1 and R required to establish a current of 50 μA in Q1.
(b) Find W2 and R2 so that Q2 operates at the edge of saturation with a current of 0.5 mA.
Page 1/3
EE330 – Homework 4 (Due: 3/31/2021 Wednesday via Canvas)
4.4 Given that a NMOS has Vt=1V, complete the table given. Operation region can be either cut off,
triode or saturation.
Page 2/3
EE330 – Homework 4 (Due: 3/31/2021 Wednesday via Canvas)
4.5 To illustrate the impact of Moore’s Law, complete the table below:
Page 3/3
EE330 HW4 Solution
4.1
4.2(a)
(b)
(c)
(d)
4.3
4.4
4.5
EE330 – Homework 3 (Due: 3/8/2021 Monday via Canvas)
First Name:
Last Name:
Red ID#:
Kindly note that no late submission will be accepted.
3.1 Assuming that the diodes in the circuits below are ideal, utilize Thévenin’s theorem to simplify
the circuits and thus find the values of the labeled currents and voltages.
3.2 A diode fed with a constant current I = 1 mA has a voltage V = 690 mV at +20°C. Find the diode
voltage
a) at −20°C
b) at +85°C.
3.3 A designer has a supply of diodes for which a current of 2 mA flows at 0.7 V. Using a 1-mA
current source, the designer wishes to create a reference voltage of 1.3 V. Note that you may use
parallel of N diodes stack that will do the job as shown. How many diodes are needed? What is the
exact voltage being achieved?
Page 1/2
EE330 – Homework 3 (Due: 3/8/2021 Monday via Canvas)
3.4 Design a diode voltage regulator to supply 1.5 V to a 1500-Ω load. Use two diodes specified to
have a 0.7-V drop at a current of 1 mA. The diodes are to be connected to a +5-V supply through a
resistor R as shown. (Hint: Use the small signal diode model to calculate all changes in ouput
voltage.)
a)
b)
c)
d)
Specify the value for R.
What is the diode current with the 1500-Ω load connected?
What is the increase resulting in the output voltage when the load is disconnected?
What change results if the load resistance is reduced to 500 Ω?
3.5 Design a 7.5-V zener regulator circuit using a 7.5-V zener specified at 10 mA. The zener has an
incremental resistance rz = 30 Ω and a knee current of 0.5 mA. The regulator operates from a 10-V
supply and has a 1.5-kΩ load.
a) What is the value of R you have chosen?
b) What is the regulator output voltage when the supply is 10% high and 10% low?
c) What is the output voltage when the supply is 10% high and the load is removed?
d) What is the smallest possible load resistor that can be used while the zener operates at a current
no lower than the knee current while the supply is 10% low? What is the load voltage in this case?
Page 2/2
EE330 HW3 Solution
3.1
3.2
3.3
3.4
(a)(b)
(c)
(d)
3.5
(a)
(b)
(c)
(d)
3/1/2021
EE 330 Fundamentals of Engineering Electronics
2
Outline
• MOSFET device characteristics
• MOSFET DC biasing
(Sedra & Smith, 8th edition, Ch 5.1-5.4, pg
244-292)
3/1/2021
EE 330 Fundamentals of Engineering Electronics
3
MOSFET and BJT
• We now switch our focus to three-terminal semiconductor
devices a.k.a transistors. With the third terminal,
transistors can provide active control compared to twoterminal devices.
• Application of transistors: Amplifiers, switches (digital logic
gates, power management), memory, *diode applications.
• MOSFET
(Metal-oxide-Semiconductor
Field-EffectTransistor) is the most dominant transistor technology,
compared to BJT (Bipolar Junction Transistor). MOSFET
can be scaled much better than BJT, consuming much
less power than BJT at a fraction of cost.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
4
MOSFET device structure
• We first look at N-channel MOSFET or NMOS, built on P-
substrate.
• Four terminals: Gate, Drain, Source, Body.
• Most critical parameters: Width (W) and Length (L).
• Core principle: Gate voltage controls Drain-Source current.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
5
MOSFET device structure
• Typically L = 0.01 μm to 1 μm, W = 0.02 μm to 100 μm,
and the thickness of the oxide layer (tox) is in the range of
1 to 10 nm.
• Also known as Insulated-gate FET (IGFET). Gate current
can be as small as order of 10−15 A.
• Parasitic PN junction are kept reverse biased  NMOS
body is connected to lowest circuit potential.
• Drain & Source are identical and symmetry physically,
defined by electrical connection.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
6
MOSFET device structure
• At zero gate bias, reverse biased PN diodes make sure
drain-source path is of high resistance (essentially off).
• Reverse biased diodes also guarantees PN junction
capacitance are kept minimal to minimize switching delay
and dynamic power loss.
• Note that MOSFET Gate-Body is essentially a capacitor.
Due to the thickness of gate SiO2 MOSFET gate capacitor
has high capacitance density.
• Body terminal is typically shared among different NMOS.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
7
NMOS I-V characteristics
• When positive VGS is applied to gate, electrons are
attracted underneath gate oxide, forming N-type channel,
also known as inversion layer (P-type property is
inverted).
• Minimal VGS value needed to sufficiently form channel =
threshold voltage Vt. (not thermal voltage). Typical Vt =
0.3V~1.0V.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
8
NMOS I-V characteristics
• “Extra” VGS applied over Vt is known as overdrive voltage
(VOV), i.e.
• Charge accumulated in the channel is:
• where (OX is permittivity of silicon dioxide.)
3/1/2021
EE 330 Fundamentals of Engineering Electronics
9
NMOS I-V characteristics
• When small VDS is applied, electrons will move and drain
current iD will flow.
• Electron drift velocity is given by:
• Total charge per unit length:
3/1/2021
EE 330 Fundamentals of Engineering Electronics
10
NMOS I-V characteristics
• Hence, NMOS drain current becomes a function of VGS and
VDS.
• Process transconductance parameters:
• Circuit design parameter: Transistor aspect ratio (W/L)
• Tip: Choose minimum L allowed for digital circuits, but
larger L for analog circuits.
3/1/2021
EE 330 Fundamentals of Engineering Electronics
11
NMOS as voltage controlled resistor
• At small VDS (
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