EEL XXXX – Integrated Circuit Technology
Target Junction Depth
Target Gate Oxide
Target Field Oxide
Worst Case Alignment Error
Minimum Separation between Metal Traces
Using the above infomration, do the following:
1) Find the appropriate value of W/L from the information above. You will need to use the
IV curve to find ID and VGS.
2) Layout the MOSFET, adhering to all separation and error parameters above.
3) Produce the SCALED and DIMENSIONED masks and a GENERAL list of process steps
required to complete the process.
1) Complete all of the steps in the undergraduate section
2) Produce a COMPLETE recipe for the proposed MOSFET, starting with a blank wafer and
ending with the MOSFET including metal contacts. These should include all
temperatures, process times, chemical recipies, cleans, equipment used, etc.
The process steps below from Figure 9-10 should be adhered to avoid overcomplication.
2.1 The Photolithographic Process
Clear glass plate
Mask in close
proximity to resist
A = 41612
Minimum-size metal-gate transistor with W/L ratio of 5/1 using the design rules of Fig. 9.11. The
active gate region is less than 5% of the total device area.
Polysilicon-Gate Transistor Layout
Transistors fabricated using polysilicon-gate technology have a number of important
advantages over those built using metal-gate processes. The polysilicon gate can with-
stand high-temperature processing following its deposition, and this significantly
improves the flexibility of the process. The silicon gate can be directly oxidized at high
temperature to form an insulating layer over the gate. The heavily doped polysilicon
represents an additional interconnect layer that other metal layers can easily cross,
because of the oxide isolation. However, the most significant advantages are in layout
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